1. Field of the Invention
The present invention relates to an output buffer and a power amplifier having the same. More particularly, the present invention relates to an output buffer having low output impedance and a power amplifier having the same.
2. Description of the Background Art
FIG. 1 is a circuit diagram of a NMOS source follower. Referring to FIG. 1, comparative low output impedance can be obtained because an output voltage Vo is obtained from a source node of a transistor MNSF. However, the output voltage Vo cannot increase higher than a value obtained by subtracting voltage drop Vgs from a gate voltage due to the voltage drop Vgs between a gate and a source. Therefore, the shown structure has a problem of a narrow swing range of the output voltage Vo.
FIG. 2 is a circuit diagram that lowers output impedance of a PMOS common source through a negative feedback using an operational transconductance amplifier (OTA). Referring to FIG. 2, it is possible to swing an output voltage until a transistor MPCS falls into a triode region because an output voltage Vo is obtained from a drain node of a transistor MPCS. That is, the output voltage may increase up to Vdd-Vdsat. Here, Vdd denotes a high level power voltage and Vdsat is an overdrive voltage. However, a PMOS common source amplifier has a shortcoming that output impedance is dynamic resistance, which is very large. Accordingly, a structure lowering impedance of an output node through a negative feedback using an operational transconductance amplifier (OTA) is introduced as shown in FIG. 2. In such a structure, output impedance is small at a low frequency zone where a gain of an OTA is large. However, output impedance becomes increased because a gain of an OTA decreases as a frequency increases. Therefore, low impedance cannot be obtained.
FIG. 3 is a circuit diagram illustrating an output stage that lowers output impendence using a negative feedback loop composed of a NMOS source follower, a PMOS common source amplifier, and a PMOS common gate amplifier. Referring to FIG. 3, the shown structure obtains very low output impedance that could not be obtained by a typical CMOS circuit by further lowering low output impedance of an NMOS source follower MNSF by connecting a NMOS source follower MNSF and a PMOS common source amplifier MPCS. The shown structure has a wide bandwidth characteristic because only one low frequency pole exists in a negative feedback loop, and very low output impedance can be sustained in a high frequency band thereby. However, a swing range of an output voltage is limited at a predetermined area as shown in FIG. 4 due to a NMOS source follower MNSF like FIG. 1 according to FIG. 3.
FIG. 4 is a graph showing an operating zone of an output electric current Io for an output voltage Vo of FIG. 3.
Referring to FIG. 4, there are four quadrants presented when relation of an output electric current Io for an output voltage Vo is illustrated. Throughout the specification, if an output stage is operable at four quadrants, it is defined as the output stage performs four-quadrant operation, and if the output stage is operable at two sections of a quadrant, it is defined as the output stage performs two-quadrant operation for convenience. Although dual supply voltage was described, single supply voltage can be applied to an output stage structure according to the present invention without changing any structure. However, an intermediate value of an output voltage is ½ of a power source voltage for a single supply voltage although an intermediate value of an output voltage is 0 for dual supply voltage.
FIG. 5 is a circuit diagram illustrating an output stage that lowers output impedance using a negative feedback loop composed of a PMOS source follower, a PMOS common source amplifier, and a NMOS common gate amplifier, and FIG. 6 is a diagram illustrating an operation zone of an output electric current Io for an output voltage Vo of FIG. 5. Referring to FIGS. 5 and 6, the output stage of FIG. 5 is different from that of FIG. 3 in which a PMOS source follower MPSF is connected to a PMOS common source amplifier MPCS. Unlike the output stage of FIG. 3 that uses a common gate amplifier formed of a PMOS transistor MP1 for forming a negative feedback loop, the output stage of FIG. 5 uses a common gate amplifier formed of a NMOS transistor MN1. Since the PMOS source follower MPSF is used, an output voltage cannot decrease a lot due to the PMOS source follower MPSF in the output stage of FIG. 5. Except that, the output stage of FIG. 5 has the same characteristics of the output stage shown in FIG. 3. FIG. 6 is a region where an output voltage is limited by a PMOS source follower MPSF.